Main menu
You are here
MONT-BLANC 2
Energy efficiency is already a primary concern for the design of any computer system and it is unanimously recognized that future Exascale systems will be strongly constrained by their power consumption. This is why the Mont-Blanc project has set itself the following objective: to design a new type of computer architecture capable of setting future global High Performance Computing (HPC) standards that will deliver Exascale performance while using 15 to 30 times less energy.
Mont-Blanc 2 contributes to the development of extreme scale energy-efficient platforms, with potential for Exascale computing, addressing the challenges of massive parallelism, heterogeneous computing, and resiliency. Mont-Blanc 2 has great potential to create new market opportunities for successful EU technology, by placing embedded architectures in servers and HPC.
FP7
This project is coordinated by the Barcelona Supercomputing Center (BSC) and has a budget of over 11 million Euros, including over 8 million Euros funded by the European Commission.
The Mont-Blanc 2 proposal has 4 objectives:
1. To complement the effort on the Mont-Blanc system software stack, with emphasis on programmer tools (debugger, performance analysis), system resiliency (from applications to architecture support), and ARM 64-bit support
2. To produce a first definition of the Mont-Blanc Exascale architecture, exploring different alternatives for the compute node (from low-power mobile sockets to special-purpose high-end ARM chips), and its implications on the rest of the system
3. To track the evolution of ARM-based systems, deploying small cluster systems to test new processors that were not available for the original Mont-Blanc prototype (both mobile processors and ARM server chips)
4. To provide continued support for the Mont-Blanc consortium, namely operations of the Mont-Blanc prototype, and hands-on support for our application developers
Mont-Blanc 2 contributes to the development of extreme scale energy-efficient platforms, with potential for Exascale computing, addressing the challenges of massive parallelism, heterogeneous computing, and resiliency. Mont-Blanc 2 has great potential to create new market opportunities for successful EU technology, by placing embedded architectures in servers and HPC.
- BSC - BARCELONA SUPERCOMPUTING CENTER - CENTRO NACIONAL DE SUPERCOMPUTACION (Spain, Coordinator)
- BULL - Bull SAS (France)
- STMicroelectronics - STMICROELECTRONICS GRENOBLE (GNB SAS) (France)
- ARM - ARM LIMITED (United Kingdom)
- JUELICH - FORSCHUNGSZENTRUM JUELICH GMBH (Germany)
- BADW-LRZ - BAYERISCHE AKADEMIE DER WISSENSCHAFTEN (Germany)
- USTUTT - UNIVERSITAET STUTTGART (Germany)
- CINECA - CONSORZIO INTERUNIVERSITARIO CINECA (Italy)
- CNRS - CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE (France)
- INRIA - INSTITUT NATIONAL DE RECHERCHE EN INFORMATIQUE ET EN AUTOMATIQUE (France)
- CEA - COMMISSARIAT A L ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
- UNIVERSITY OF BRISTOL - UNIVERSITY OF BRISTOL (United Kingdom)
- ALLINEA SW LIM - ALLINEA SOFTWARE LIMITED (United Kingdom)